Metro-on-chip: an efficient physical design technique for congestion reduction
نویسندگان
چکیده
منابع مشابه
Metro-on-chip: an efficient physical design technique for congestion reduction
Routing congestion is one of the main factors in designing in deep submicron technology that may cause unroutability of the design, signal integrity problems and large delays in detoured wires. In this paper, a new methodology is presented which multiplexes regular nets by asynchronous serial transceivers in the physical design flow in order to improve the congestion of the design. Experimental...
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Routability, signal integrity and manufacturability are important issues in physical design and congestion reduction is a widely used method for ameliorating these problems in current design methodologies. Besides, routing congestion may create large delays in detoured global wires that can be avoided by congestion reduction. In recent years, asynchronous serial transceivers are proposed for da...
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Effective and congestion-aware routing is vital to the performance of network-on-chip. The efficient routing algorithm undoubtedly relies on the considered selection strategy. If the routing function returns a number of more than one permissible output ports, a selection function is exploited to choose the best output port to reduce packets latency. In this paper, we introduce a new selection s...
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ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2007
ISSN: 1349-2543
DOI: 10.1587/elex.4.510